(1) Field of the Invention
The present invention relates to a method of forming semiconductor structures, and more particularly, to a method of forming capacitance node contacts in the dynamic random access memory (DRAM) fabrication process.
(2) Description of the Prior Art
DRAM memory cells are a well-known class of semiconductor devices in the art. These devices provide a means of temporary data storage, and they are used in many digital systems, such as computers.
Because of intense competition in the DRAM marketplace, it is essential that manufacturers reduce the cost of their DRAM memory circuits. To reduce costs and to meet customer expectations for decreasing access times and increasing IC memory sizes, manufacturers must continually reduce the size of features on the integrated circuit wafer. Such reductions in feature size have brought about much advancement in the art. However, the small geometries present problems in the predictable manufacture of DRAM circuits.
One manufacturing problem is illustrated in the partially completed prior art DRAM cell depicted in cross-section in FIG. 1. In this schematic, typical layers for a DRAM are shown. The cell contains a substrate 11 typically composed of lightly doped P-type monocrystalline silicon. A thin layer of gate oxide 12 overlays the substrate surface. A polysilicon layer 13 overlays the gate oxide 12 and both layers have been patterned to form the two transistor gates depicted. A gate cap 14 and sidewall spacer 16, each of silicon nitride, insulate the gate structures. The transistor source and drain regions in the substrate contain a lightly doped N-type region 15 and a heavily doped N-type region 17. Overlying the gates are silicon oxide layers 18 and 20 and 22. A polysilicon plug 19 fills the region between the two transistor gates and contacts the surface of the substrate 11. Two polysilicon bit lines 21 are shown. A silicon nitride liner layer 23 typically isolates the polysilicon capacitance node 24 from the bit lines 21.
In the example, however, the capacitance node 24 is shorted to the bit line 21 at location 25. This short effectively disables the function of the DRAM cell. The manufacturing problem that caused the short was a large misalignment between the polysilicon bit lines 21 and the contact hole for the polysilicon capacitor node 24. Because of the misalignment, the silicon nitride liner layer 23 did not cover all of the polysilicon bit line 21 after the dry etch step. This manufacturing problem occurs most often at process geometries of less than 0.25 microns, when the specifications become very tight.
Several prior art approaches attempt to reduce the likelihood or severity of shorts between the capacitor node and the bit lines. U.S. Pat. No. 5,763,306 to Tsai shows the conventional contact hole etch. In this invention, a silicon nitride layer overlays the bit line to act as a stop layer in the contact etch. U.S. Pat. No. 5,545,584 to Wuu et al teaches another conventional contact process. U.S. Pat. No. 5,770,498 to Becker shows the conventional contact node etch with no liner. U.S. Pat. No. 5,789,291 to Sung teaches the use of oxide sidewall spacers to line the contact hole used to form the DRAM capacitor.